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A42L2604 Series
Preliminary
Document Title 4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE Revision History
Rev. No.
0.0 0.1 0.2 0.3
4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE
History
Initial issue Modify symbol HE dimensions in TSOP 24L package information Add -45 grade and modify the AC, DC data Add -U type spec. Modify DC data and all parts guarantee self-refresh mode
Issue Date
June 13, 2001 July 10, 2001 November 30, 2001 June 10, 2002
Remark
Preliminary
PRELIMINARY (June, 2002, Version 0.3)
AMIC Technology, Inc.
A42L2604 Series
Preliminary
Features
n Organization: 4,194,304 words X 4 bits n Part Identification - A42L2604 (2K Ref.) n Single 3.3V power supply/built-in VBB generator n Low power consumption - Operating: 80mA (-45 max) - Standby: 1.0mA (TTL), 1.5mA (CMOS), 350A (Self-refresh current) n High speed - 45/50 ns RAS access time - 20/22 ns column address access time - 12/13 ns CAS access time - 18/20 ns EDO Page Mode Cycle Time n Industrial operating temperature range: -40C to +85C for -U n Fast Page Mode with Extended Data Out n 2K Refresh Cycle in 32ms n Read-modify-write, RAS -only, CAS -before- RAS , Hidden refresh capability n TTL-compatible, three-state I/O n JEDEC standard packages - 300mil, 24/26-pin SOJ - 300mil, 24/26-pin TSOP type II package
4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE
General Description
The A42L2604 is a new generation randomly accessed memory for graphics, organized in a 4,194,304-word by 4-bit configuration. This product can execute Write and Read operation via CAS pin. The A42L2604 offers an accelerated Fast Page Mode cycle with a feature called Extended Data Out (EDO). This allow random access of up to 2048(2K Ref.) words within a row at a 56/50 MHz EDO cycle, making the A42L2604 ideally suited for graphics, digital signal processing and high performance computing systems.
Pin Configuration n SOJ n TSOP Pin Descriptions
26 25 24 23 VSS I/O3 I/O2 CAS OE A9
VCC I/O0 I/O1 WE RAS NC
1 2 3 4
26 25 24 23
VSS I/O3 I/O2 CAS OE A9
VCC I/O0 I/O1 WE RAS NC
1 2 3 4
Symbol A0 - A10 I/O0 - I/O3 RAS
Description Address Inputs (2K product) Data Input/Output Row Address Strobe Column Address Strobe Write Enable Output Enable 3.3V Power Supply Ground No Connection
A42L2604S
A42L2604V
5 6
22 21
5 6
22 21
CAS
19 18 17 16 15 14 A8 A7 A6 A5 A4 VSS
A10 A0 A1 A2 A3 VCC
8 9 10 11 12 13
19 18 17 16 15 14
A8 A7 A6 A5 A4 VSS
A10 A0 A1 A2 A3 VCC
8 9 10 11 12 13
WE
OE VCC VSS NC
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A42L2604 Series
Selection Guide
Symbol tRAC tAA tCAC tOEA tRC tPC Description Maximum RAS Access Time Maximum Column Address Access Time Maximum CAS Access Time Maximum Output Enable ( OE ) Access Time Minimum Read or Write Cycle Time Minimum EDO Cycle Time -45 45 20 12 12 76 18 -50 50 22 13 13 84 20 Unit ns ns ns ns ns ns
Functional Description
The A42L2604 reads and writes data by multiplexing an 22-bit address into a 11-bit(2K) row and column address. RAS and CAS are used to strobe the row address and the column address, respectively. A Read cycle is performed by holding the WE signal high during RAS / CAS operation. A Write cycle is executed by holding the WE signal low during RAS / CAS operation; the input data is latched by the falling edge of WE or CAS , whichever occurs later. The data inputs and outputs are routed through 4 common I/O pins, with RAS , CAS , WE and OE controlling the in direction. EDO Page Mode operation all 2048(2K) columns within a selected row to be randomly accessed at a high data rate. A EDO Page Mode cycle is initiated with a row address latched by RAS followed by a column address latched by CAS . While holding RAS low, CAS can be toggled to strobe changing column addresses, thus achieving shorter cycle times. The A42L2604 offers an accelerated Fast Page Mode cycle through a feature called Extended Data Out, which keeps the output drivers on during the CAS precharge time (tcp). Since data can be output after CAS goes high, the user is not required to wait for valid data to appear before starting the next access cycle. Data-out will remain valid as long as RAS and OE are low, and WE is high; this is the only characteristic which differentiates Extended Data Out operation from a standard Read or Fast Page Read. A memory cycle is terminated by returning both RAS and CAS high. Memory cell data will retain its correct state by maintaining power and accessing all 2048(2K) combinations of the 11-bit(2K) row addresses, regardless of sequence, at least once every 32ms through any RAS cycle (Read, Write) or RAS Refresh cycle ( RAS -only, CBR, or Hidden). The CBR Refresh cycle automatically controls the row addresses by invoking the refresh counter and controller.
Power-On
The initial application of the VCC supply requires a 200 s wait followed by a minimum of any eight initialization cycles containing a RAS clock. During Power-On, the VCC current is dependent on the input levels of RAS and CAS . It is recommended that RAS and CAS track with VCC or be held at a valid VIH during Power-On to avoid current surges.
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A42L2604 Series
Block Diagram
RAS CAS WE
Vcc Control Clocks VBB Generator Vss
Refresh Timer
Row Decoder Data in Buffer Sense Amps & I/O
Refresh control Memory Array 4,194,304 X 4 Cells
I/O0 to I/O3
Refresh Counter
Data out Buffer
OE
A0~A10
Row Address Buffer
A0~A10
Col. Address Buffer
Column Decoder
Recommended Operating Conditions
Symbol VCC VSS VIH VIL Description Power Supply Input High Voltage Input High Voltage Input Low Voltage
(Ta = 0C to +70C or -40C to +85C) Min. 3.0 0 2.0 -0.5 Typ. 3.3 0 Max. 3.6 0 VCC + 0.3 0.8 Unit V V V V
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Truth Table
Function Standby Read: Word Read Write: Word (Early) Write (Early) Read-Write EDO-Page-Mode Read: Hi-Z -First cycle -Subsequent Cycles EDO-Page-Mode Write (Early) -First cycle -Subsequent Cycles EDO-Page-Mode Read-Write -First cycle -Subsequent Cycles Hidden Refresh Read Hidden Refresh Write RAS -Only Refresh CBR Refresh Self Refresh RAS H L L L L L L L L L L L LHL LHL L HL HL
CAS
H L L L L L HL HL HL HL HL HL L L H L L
WE X H H L L HL H H L L HL HL H L X X H
OE X L L X X LH HL HL X X LH LH L X X X X
Address X Row/Col. Row/Col. Row/Col. Row/Col. Row/Col. Row/Col. Col. Row/Col. Col. Row/Col. Col. Row/Col. Row/Col. Row X X
I/Os High-Z Data Out Data Out Data In Data In Data Out Data In Data Out Data Out Data In Data In Data Out Data In Data Out Data In Data Out Data In High-Z High-Z High-Z High-Z
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A42L2604 Series
Absolute Maximum Ratings*
Input Voltage (Vin) . . . . . . . . . . . . . . . . . . . -0.5V to +4.6V Output Voltage (Vout) . . . . . . . . . . . . . . . . -0.5V to +4.6V Power Supply Voltage (VCC) . . . . . . . . . . . -0.5V to +4.6V Operating Temperature (TOPR) . . . . . . . . . . 0C to +70C Storage Temperature (TSTG) . . . . . . . . . -55C to +150C Soldering Temperature X Time (TSOLDER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C X 10sec Power Dissipation (PD) . . . . . . . . . . . . . . . . . . . . . . . . 1W Short Circuit Output Current (Iout) . . . . . . . . . . . . . 50mA Latch-up Current . . . . . . . . . . . . . . . . . . . . . . . . . . 200mA
*Comments
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of these specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
DC Electrical Characteristics (VCC = 3.3V 0.3V, VSS = 0V, Ta = 0C to +70C or -40C to +85C)
-45 Symbol IIL Parameter Min. Input Leakage Current -5 Max. +5 Min. -5 Max. +5 A 0V Vin Vin + 0.3V Pins not under Test = 0V DOUT disabled, 0V Vout + VCC RAS , UCAS , LCAS and Address cycling; tRC = min. RAS = UCAS = LCAS =VIH RAS and Address cycling, UCAS = LCAS = VIH, tRC = min. RAS = VIL, UCAS , LCAS and Address cycling; tPC = min. RAS , UCAS and LCAS cycling; tRC = min. RAS = UCAS = LCAS = VCC - 0.2V RAS = CAS VSS+0.2V All other input high levels are VCC-0.2V or input low levels are VSS +0.2V IOUT = -2.0mA IOUT =2.0mA 1 1, 2 -50 Unit Test Conditions Notes
IOL ICC1
Output Leakage Current Operating Power Supply Current TTL Standby Power Supply Current Average Power Supply Current, RAS Refresh Mode EDO Page Mode Average Power Supply Current CAS -before- RAS Refresh Power Supply Current CMOS Standby Power Supply Current Self Refresh Mode Current
-5 -
+5 80
-5 -
+5 75
A mA
ICC2 ICC3
-
1.5 80
-
1.5 75
mA mA
ICC4
-
80
-
75
mA
1, 2
ICC5
-
80
-
75
mA
1
ICC6
-
1.0
-
1.0
mA A
ICC7
-
350
-
350
VOH VOL Output Voltage
2.4 -
0.4
2.4 -
0.4
V V
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A42L2604 Series
AC Characteristics (VCC = 3.3V 0.3V, VSS = 0V, Ta = 0C to +70C or -40C to +85C)
Test Conditions: Input timing reference level: VIH/VIL=2.0V/0.8V Output reference level: VOH/VOL=2.0V/0.8V Output Load: 2TTL gate + CL (50pF) Assumed tT=2ns Std Symbol tT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 tRC tRP tRAS tCAS tRCD tRAD tRSH tCSH tCRP tASR tRAH tCLZ tRAC tCAC tAA tOEA tAR tRCS tRCH -45 Parameter Min. Transition Time (Rise or Fall) Random Read or Write Cycle Time RAS Precharge Time RAS Pulse Width CAS Pulse Width RAS to CAS Delay Time RAS to Column Address Delay Time CAS to RAS Hold Time CAS Hold Time CAS to RAS Precharge Time Row Address Setup Time Row Address Hold Time CAS to Output in Low Z Access Time from RAS Access Time from CAS Access Time from Column Address Access Time from OE Column Address Hold Time from RAS Read Command Setup Time Read Command Hold Time 1 76 27 45 7 10 8 7 35 5 0 7 3 40 0 0 Max. 50 10K 10K 33 25 45 12 20 12 Min. 1 84 30 50 8 11 9 8 37 5 0 8 3 45 0 0 Max. 50 10K 10K 37 28 50 13 22 13 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 9 8 6,7 6, 12 7, 12 6 7 4, 5 -50 Unit Notes
#
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AC Characteristics (continued) (VCC = 3.3V 0.3V, VSS = 0V, Ta = 0C to +70C or -40C to +85C)
Test Conditions: Input timing reference level: VIH/VIL=2.0V/0.8V Output reference level: VOH/VOL=2.0V/0.8V Output Load: 2TTL gate + CL (50pF) Assumed tT=2ns Std Symbol tRRH tRAL TCOH tOFF tASC tCAH tOES tWCS tWCH tWCR tWP tRWL tCWL tDS tDH tDHR tRWC tRWD tCWD tAWD -45 Parameter Min. 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Read Command Hold Time Reference to RAS Column Address to RAS Lead Time Output Hold After CAS Low Output Buffer Turn-Off Delay Time Column Address Setup Time Column Address Hold Time
OE Low to CAS High Set Up
-50 Unit Max. 2 Min. 0 22 3 0 8 10 0 8 45 8 13 8 0 8 45 114 65 28 37 Max. 3 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 11 11 11 11 11 8, 10 9 Notes
#
0 20 2 0 7 10 0 7 40 7 12 7 0 7 40 104 59 26 34
Write Command Setup Time Write Command Hold Time Write Command Hold Time to RAS Write Command Pulse Width Write Command to RAS Lead Time Write Command to CAS Lead Time Data-in setup Time Data-in Hold Time Data-in Hold Time to RAS Read-Modify-Write Cycle Time RAS to WE Delay Time (Read-Modify-Write) CAS to WE Delay Time (Read-Modify-Write) Column Address to WE Delay Time (Read-Modify-Write)
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AC Characteristics (continued) (VCC = 3.3V 0.3V, VSS = 0V, Ta = 0C to +70C or -40C to +85C)
Test Conditions: Input timing reference level: VIH/VIL=2.0V/0.8V Output reference level: VOH/VOL=2.0V/0.8V Output Load: 2TTL gate + CL (50pF) Assumed tT=2ns Std Symbol tOEH tOEP tPC tCPA tCP tPCM tCRW tRASP tCSR tCHR tRPC tOEZ tRASS tRPS tCHS -45 Parameter Min. 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 OE Hold Time from WE OE High Pulse Width Read or Write Cycle Time (EDO Page) Access Time from CAS Precharge (EDO Page) CAS Precharge Time EDO Page Mode RMW Cycle Time EDO Page Mode CAS Pulse Width (RMW) RAS Pulse Width (EDO Page) 7 46 35 45 5 10 10 100 76 -50 200K 2 8 50 38 50 5 10 10 100 84 -50 200K 3 ns ns ns ns ns ns ns ns s ns ns 8 3 3 7 5 18 Max. 21 Min. 8 5 20 Max. 23 ns ns ns ns 13 12 -50 Unit Notes
#
CAS Setup Time ( CAS -before- RAS ) CAS Hold Time ( CAS -before- RAS )
RAS to CAS Precharge Time Output Buffer Turn-off Delay from OE RAS pulse width ( C -B-R self refresh) RAS precharge time ( C -B-R self refresh) CAS hold time ( C -B-R self refresh)
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Notes: 1. ICC1, ICC3, ICC4, and ICC5 depend on cycle rate. 2. ICC1 and ICC4 depend on output loading. Specified values are obtained with the outputs open. 3. An initial pause of 200s is required after power-up followed by any 8 RAS cycles before proper device operation is achieved. In the case of an internal refresh counter, a minimum of 8 CAS -before- RAS initialization cycles instead of 8 RAS cycles are required. 8 initialization cycles are required after extended periods of bias without clocks. 4. AC Characteristics assume tT = 2ns. All AC parameters are measured with a load equivalent to two TTL loads and 50pF, VIL (min.) GND and VIH (max.) VCC. 5. VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL. 6. Operation within the tRCD (max.) limit insures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled exclusively by tCAC. 7. Operation within the tRAD (max.) limit insures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled exclusively by tAA. 8. Assumes three state test load (5pF and a 500 Thevenin equivalent). 9. Either tRCH or tRRH must be satisfied for a read cycle. 10. tOFF (max.) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels. 11. tWCS, tWCH, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS tWCS (min.) and tWCH tWCH (min.), the cycle is an early write cycle and data-out pins will remain open circuit, high impedance, throughout the entire cycle. If tRWD tRWD (min.) , tCWD tCWD (min.) and tAWD tAWD (min.), the cycle is a read-modify-write cycle and the data out will contain data read from the selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate. 12. Access time is determined by the longer of tAA or tCAC or tCPA. 13. tASC tCP to achieve tPC (min.) and tCPA (max.) values.
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Word Read Cycle
tRC(1) tRAS(3) tRP(2)
RAS
tCSH(8) tCRP(9) tRCD(5) tRSH(7) tCAS(4) tCRP(9)
CAS
tRAD(6) tASR(10) tRAH(11) tASC(24) tRAL(21) tCAH(25)
Address
Row Address
tAR(17)
Column Address
tRCH(19) tRRH(20)
tRCS(18)
WE
tOEA(16)
OE
tCAC(14) tAA(15) tRAC(13) tOFF(23) tOEZ(51)
I/O 0 ~ I/O 3
High-Z
tCLZ(12)
Valid Data-out
: High or Low
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Word Write Cycle (Early Write)
tRC(1) tRAS(3) tRP(2)
RAS
tCSH(8) tCRP(9) tRCD(5) tRSH(7) tCAS(4) tCRP(9)
CAS
tAR(17) tRAD(6) tASR(10) tRAH(11) tASC(24)
tRAL(21) tCAH(25)
Address
Row Address
Column Address
tWCR(29) tCWL(32) tRWL(31) tWP(30)
WE
tWCS(27) tWCH(28)
OE
tDHR(35) tDS(33) tDH(34)
I/O0 ~ I/O3
Valid Data-in
: High or Low
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Word Write Cycle (Late Write)
tRC(1) tRAS(3) tRP(2)
RAS
tCSH(8) tCRP(9) tRCD(5) tRSH(7) tCAS(4) tCRP(9)
CAS
tAR(17) tRAD(6) tASR(10) tRAH(11) tASC(24)
tRAL(21) tCAH(25)
Address
Row Address
Column Address
tCWL(32) tRWL(31) tWCR(29) tWP(30)
WE
tOEH(40)
OE
tDHR(35) tDS(33) tDH(34)
I/O0 ~ I/O3
High-Z Vaild Data-in
: High or Low
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Word Read-Modify-Write Cycle
tRWC(36) tRAS(3) tRP(2)
RAS
tCSH(8) tCRP(9) tRCD(5) tRSH(7) tCRP(9)
CAS
tAR(17) tRAD(6) tASR(10) tRAH(11) tASC(24) tCAH(25)
Address
Row Address
Column Address
tAWD(39) tRCS(18) tRWD(37) tCWD38) tCWL(32) tRWL(31)
WE
tWP(30) tOEA(16) tOEZ(51)
OE
tCAC(14) tAA(15) tRAC(13) tDS(33) tOEH(40) tDH(34)
I/O 0 ~ I/O 3
High-Z Data-out
tCLZ(12)
Data-in
: High or Low
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EDO Page Mode Word Read Cycle
tRASP(47)
tRP(2)
RAS
tCSH(8) tCRP(9) tRCD(5) tCAS(4) tCP(44) tPC(42) tCAS(4) tRSH(7) tCRP(9) tCAS(4)
CAS
tCSH(8) tAR(16) tASR(10) tRAD(6) tRAH(11) tCAH(25) tASC(24) tRAL(21) tCAH(25) tASC(24)
Address
Row
Column
tCAH(25) tRCS(18)
Column
tRCS(18) tRCH(25)
Column
tRCS(18) tRCH(19)
WE
tAA(15) tCPA(43) tOEA(16) tOEA(16) tOES(26) tCAC(14) tCAC(14) tCLZ(12) tCOH(22) tAA(15) tRRH(20)
OE
tRAC(13)
tOEP(41) tCAC(14) tOEZ(51)
tOFF(23) tOEZ(51)
I/O 0 ~ I/O 3
Data-out
Data-out
Data-out
tCLZ(12)
: High or Low
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EDO Page Mode Early Word Write Cycle
tRASP(47)
tRP(2)
RAS
tCSH(8) tCRP(9) tRCD(5) tCAS(4) tCP(44) tCAS(4) tCP(44) tCAS(4) tPC(42) tRSH(7) tCRP(9)
CAS
tRAL(21) tRAD(6) tASR(10) tRAH(11) tASC(24) tCAH(25) tASC(24) tCAH(25) tASC(24) tCAH(25)
Address
Row
Column
tCWL(32) tWCS(27) tWCS(27) tWCH(28)
Column
tCWL(32) tWCS(27) tWCH(28)
Column
tCWL(32) tRWL(31) tWCH(28)
WE
tWP(30) tWP(30) tWP(30)
OE
tDH(34) tDS(33) tDS(33)
tDH(34) tDS(33)
tDH(34)
I/O 0 ~ I/O 3
Data-in
Data-in
Data-in
: High or Low
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EDO Page Mode Word Read-Modify-Write Cycle
tRASP(47)
tRP(2)
RAS
tCSH(8) tRCD(5) tCRW(46) tCP(44) tCRW(46) tCP(44) tCRW(46) tPCM(45) tRSH(7) tCRP(9)
tCRP(9)
CAS
tRAD(6) tASR(10) tRAH(11) tCAH(25) tASC(24) tCAH(25) tASC(24) tRAL(21) tCAH(25) tASC(24)
Address
Row
Column
Column
tCWL(32)
Column
tCWL(32) tCWL(32) tRWL(31)
tRWD(37) tRCS(18) tCWD(38) tCWD(38) tCWD(38)
WE
tWP(30) tAWD(39) tAWD(39) tWP(30) tAWD(39) tWP(30)
tOEA(16)
tOEA(16) tOEH(40)
tOEA(16)
OE
tCAC(14) tAA(15) tOEZ(51) tRAC(13)
tCPA(43) tAA(15) tOEZ(51) tDH(34) tDS(33)
tCPA(43) tAA(15) tOEZ(51) tDH(34) tDS(33) tDH(34) tDS(33)
I/O0 ~ I/O 3
High-Z
tCLZ(12) tCLZ(12) tCLZ(12)
Data-in Data-out Data-out
Data-in Data-out
Data-in
: High or Low
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RAS Only Refresh Cycle
tRC(1) tRAS(3) tRP(2)
RAS
tRPC(50)
tCRP(9)
CAS
tASR(10) tRAH(11)
Address
Row
Note: WE, OE = Don't care.
: High or Low
CAS Before RAS Refresh Cycle
tRC(1) tRP(2) tRAS(3) tRP(2)
RAS
tRPC(50) tPC(44) tCSR(48) tCHR(49)
CAS
tOFF(23)
I/O 0 ~ I/O 3
High-Z
Note: WE, OE, Address = Don't care.
: High or Low
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Hidden Refresh Cycle (Word Read)
tRC(1) tRAS(3) tRP(2) tRAS(3) tRC(1) tRP(2)
RAS
tAR(17) tCRP(9) tRCD(5) tRSH(7) tCHR(49) tCRP(9)
UCAS LCAS
tASR(10) tRAD(6) tRAH(11) tASC(24) tRAL(21) tCAH(25)
A0~A8
Row
Column
tRCS(18)
tRRH(20)
WE
tAA(15) tOEZ(51) tOEA(16)
OE
tCAC(14) tCLZ(12) tRAC(13)
tOFF(23)
I/O0 ~ I/O15
High-Z Valid Data-out
: High or Low
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Hidden Refresh Cycle (Early Word Write)
tRC(1) tRAS(3) tRP(2) tRAS(3)
tRC(1) tRP(2)
RAS
tAR(17) tCRP(9) tRCD(5) tRSH(7) tCHR(49) tCRP(9)
CAS
tRAD(6) tASR(10) tRAH(11) tASC(24)
tRAL(21) tCAH(25)
Address
Row
tWCS(27)
Column
tWCH(28) tWP(30)
WE
OE
tDS(33)
tDH(34)
I/O 0 ~ I/O 3
Valid Data-in
: High or Low
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EDO Page Mode Read-Early-Write Cycle (Pseudo Read-Modify-Write)
tRASP(47)
tRP(2)
RAS
tCSH(8) tPC(42) tCRP(9) tRCD(5) tCAS(4) tCP(44) tCAS(4) tPC(42) tCP(44) tRSH(7) tCAS(4) tCPR(9)
CAS
tRAL(21) tRAD(6) tASR(10) tRAH(11) tASC(24) tCAH(25) tASC(24) tCAH(25) tASC(24) tCAH(25)
Address
Row
Column
Column
tRCH(19)
Column
tRCS(18) tWCS(27) tWCH(28)
WE
tAA(15) tRAC(13) tCAC(14) tOEA(16)
tAA(15) tCAP(43) tCAC(14) tDS(33) tDH(34)
OE
tCOH(22)
I/O0 ~ I/O3
Data-out
Data-out
Data-in
: High or Low
PRELIMINARY
(June, 2002, Version 0.3)
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AMIC Technology, Inc.
A42L2604 Series
Self Refresh Mode
tRP(2)
tRASS(52)
tRPS(53)
RAS
tRPC(50)
tCSR(48)
tCHS(54)
tCRP(9)
UCAS LCAS
tCP(44) tASR(10)
A0 ~ A10
tOFF(23)
ROW
COL
I/O0 ~ I/O3
High-Z
Note: WE, OE = Don't care.
: High or Low
n Self Refresh Mode. a. Entering the Self Refresh Mode: The A42L2604 Self Refresh Mode is entered by using CAS before RAS cycle and holding RAS and CAS signal "low" longer than 100s. b. Continuing the Self Refresh Mode: The Self Refresh Mode is continued by holding RAS "low" after entering the Self Refresh Mode. It does not depend on CAS being "high" or "low" after entering the Self Refresh Mode continue the Self Refresh Mode. c. Exiting the Self Refresh Mode: The A42L2604 exits the Self Refresh Mode when the RAS signal is brought "high".
PRELIMINARY
(June, 2002, Version 0.3)
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AMIC Technology, Inc.
A42L2604 Series
Capacitance (f = 1MHz, Ta = Room Temperature, VCC = 3.3V 10%)
Symbol CIN1 CIN2 Signals A0 - A10 RAS , CAS , WE , OE CI/O I/O0 - I/O3 I/O Capacitance 7 pF Vin = Vout = 0V Input Capacitance Parameter Max. 5 7 Unit pF pF Test Conditions Vin = 0V Vin = 0V
Ordering Codes
Package RAS Access Time SOJ 24/26L (300mil) TSOP 24/26L type II (300mil) TSOP 24/26L type II (300mil) 45ns A42L2604S-45 A42L2604V-45 A42L2604V-45U 50ns A42L2604S-50 A42L2604V-50 A42L2604V-50U Refresh Cycle 2K 2K 2K Self-Refresh Yes Yes Yes
Note: -U is for industrial operating temperature range.
PRELIMINARY
(June, 2002, Version 0.3)
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AMIC Technology, Inc.
A42L2604 Series
Package Information SOJ 24/26L (300mil) Outline Dimensions
unit: inches/mm
D 24 19 18 13
E1 1 Pin 1 Identifier 6 7 12
E
A2
A
A1
A E2
A
-yS
b b2
e
0.004 y
Seating Plane
Symbol
A A1 A2 b b2 C D E E1 E2 e S
Dimensions in inches Min 0.070 0.095 0.016 0.026 0.008 0.327 0.295 0.245 0.044 0 Nom 0.080 0.100 0.018 0.028 0.010 0.675 0.337 0.300 0.265 0.050 Max 0.140 0.090 0.105 0.022 0.032 0.014 0.686 0.347 0.305 0.285 0.056 0.048 10
Dimensions in mm Min 1.78 2.41 0.41 0.66 0.20 8.31 7.49 6.22 1.12 0 Nom 2.03 2.54 0.46 0.71 0.25 17.15 8.56 7.62 6.73 1.27 Max 3.56 2.29 2.67 0.56 0.81 0.36 17.42 8.81 7.75 7.24 1.42 1.22 10
Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E1 does not include resin fins. 3. Dimension E2 is for PC Board surface mount pad pitch design reference only. 4. Dimension S includes end flash.
PRELIMINARY
(June, 2002, Version 0.3)
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AMIC Technology, Inc.
C
A42L2604 Series
Package Information TSOP 24/26L (TYPE II) (300mil) Outline Dimensions
24 13
unit: inches/mm
HE
E
0.010
L1
1
D
12
A2
A1
D
S
e
B
A
y
L1
L
Dimensions in inches Symbol A A1 A2 B c D E e HE L L1 S y Min 0.002 0.037 0.012 0.671 0.298 0.355 0.016 0 Nom 0.039 0.016 0.005 0.675 0.300 0.050 0.363 0.031 0.020 0.037 Max 0.047 0.041 0.020 0.679 0.302 0.371 0.024 0.004 5
Dimensions in mm Min 0.05 0.95 0.30 17.04 7.57 9.02 0.40 0 Nom 1.00 0.40 0.127 17.14 7.62 1.27 9.22 0.80 0.50 0.95 Max 1.20 1.05 0.50 17.24 7.67 9.42 0.60 0.10 5
Notes: 1. Dimension D&E do not included interlead flash. 2. Dimension B does not included dambar protrusion / intrusion. 3. Dimension S includes end flash.
PRELIMINARY
(June, 2002, Version 0.3)
24
AMIC Technology, Inc.
c

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